The said digital gate circuit macro model can be used to perform a logical simulation for gate circurit and the digital circuit formed by the gate circuit.
GFMS is a Gate and Function Block of mixed-level simulation system, which is designed for experiment of Digital Logical.
GFMS是针对《数字逻辑》课程实验而设计的数学电路模拟系统。
3
We focus on the carrier synchronization method, the circuit and its parameters design, the performance simulation and the circuit implementation in Field Programmable Gate Array (FPGA).