CPU multiplier

（重定向自Clock doubling）

Topology of an older x86 computer. Notice the FSB connecting the CPU and the northbridge.

In computing, the clock multiplier (or CPU multiplier or bus/core ratio) measures the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency multiplier circuitry) for every external clock cycle. For example, a system with an external clock of 133 MHz and a 10x clock multiplier will have an internal CPU clock of 1.33 GHz. The external address and data buses of the CPU (often collectively termed front side bus or FSB in PC contexts) also use the external clock as a fundamental timing base; however, they could also employ a (small) multiple of this base frequency (typically two or four) in order to transfer data faster.

单词	Clock doubling
释义	Clock doubling 英语百科 CPU multiplier （重定向自Clock doubling） In computing, the clock multiplier (or CPU multiplier or bus/core ratio) measures the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency multiplier circuitry) for every external clock cycle. For example, a system with an external clock of 133 MHz and a 10x clock multiplier will have an internal CPU clock of 1.33 GHz. The external address and data buses of the CPU (often collectively termed front side bus or FSB in PC contexts) also use the external clock as a fundamental timing base; however, they could also employ a (small) multiple of this base frequency (typically two or four) in order to transfer data faster.
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