At the end of the counting period, the main gate is closed and counter reset for the next sampling period.
在计数阶段的最后，主控门关闭，然后计数器复位，开始下一个采样阶段。
2
Cymometer gate circuit and by the time counter composition.
频率计由时间闸门电路和计数器组成。
3
Based on the working principle, counter structure and Clocked Transmission Gate Adiabatic Logic circuits, a design scheme of decimal counter with reset is proposed.