This design facilitates voltage control of a transmissionbus.
此设计使输电母线易于电压控制。
2
These may be required where harmonic currents caused by the thyristor phase control of the reactor current must be filtered to prevent unacceptable transmissionbus voltage distortion.
这里须滤去由电抗器相位控制引起的谐波电流以避免不能接受的输电母线电压畸变。
3
Click on the Default Common event Infrastructure event bustransmission.