This paper introduces the design thought of a wide band digital frequency synthesisloop. The principle circuit is given.
介绍了一种宽带数字式频率合成环路的设计思想,给出了原理电路。
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In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.