英语词汇on-chip memory怎么读，是什么意思，单词翻译、读音、固定搭配用法和短语词组及例句-英汉双解词典

单词

on-chip memory

释义

on-chip memory

简明释义

单片存储器
片上存储器

网络释义

1
?片上存储器
嵌入式MPSoC的片上存储器设计优化技术综述 - 存储技术 - 优领域 - 在优领域，找到您想要的！关键词 MPSoC；片上存储器；SPM；Cache；设计优化[gap=733]Keywords MPSoC；On-chip Memory；SPM；Cache；Design
2
?片内存储器
... On-Chip Debug On-Chip 调试 on-chip memory 片内存储器 Pad Placement 垫布局 ...
3
?晶载记忆体
... off-chip memory 片外存储器 ; 片外内存 ; 记忆体 on-chip memory 晶载记忆体 logic-in-memory chip 存储器内逻辑芯片 ...

短语

1
on chip memory
单片存储器
2
on-chip memory logic
片上存储器逻辑 ; 上存储器逻辑
3
On-Chip Memory Controller
上存储器控制器

双语例句

1
The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP's on-chip memory.
针对DSP片内资源特点设计了片内存储器数据分配方案，并根据该方案优化了MPEG 4视频压缩的数据流模式。
2
In this paper, an allocation strategy for on-chip memory is proposed to optimize energy of memory system.
提出一种基于能耗热点的片上存储器静态分配策略。
3
Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).
由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。

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英汉双解词典包含3185865条英汉词条，基本涵盖了全部常用单词的翻译及用法，是英语学习的有利工具。

单词	on-chip memory
释义	on-chip memory 简明释义单片存储器片上存储器网络释义 1 ?片上存储器嵌入式MPSoC的片上存储器设计优化技术综述 - 存储技术 - 优领域 - 在优领域，找到您想要的！关键词 MPSoC；片上存储器；SPM；Cache；设计优化[gap=733]Keywords MPSoC；On-chip Memory；SPM；Cache；Design 2 ?片内存储器 ... On-Chip Debug On-Chip 调试 on-chip memory 片内存储器 Pad Placement 垫布局 ... 3 ?晶载记忆体 ... off-chip memory 片外存储器 ; 片外内存 ; 记忆体 on-chip memory 晶载记忆体 logic-in-memory chip 存储器内逻辑芯片 ... 短语 1 on chip memory 单片存储器 2 on-chip memory logic 片上存储器逻辑 ; 上存储器逻辑 3 On-Chip Memory Controller 上存储器控制器双语例句 1 The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP's on-chip memory. 针对DSP片内资源特点设计了片内存储器数据分配方案，并根据该方案优化了MPEG 4视频压缩的数据流模式。 2 In this paper, an allocation strategy for on-chip memory is proposed to optimize energy of memory system. 提出一种基于能耗热点的片上存储器静态分配策略。 3 Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1). 由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。
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