时钟门控

时钟门控（英语：Clock gating）是一种在同步时序逻辑电路的一种定时器信号技术，可以降低芯片功耗。时钟门控通过在电路中增加额外的逻辑单元、优化时钟树结构来节省电能。

可以通过以下几种方式在设计中添加时钟门控逻辑：

单词	Clock gating
释义	Clock gating 中文百科时钟门控时钟门控（英语：Clock gating）是一种在同步时序逻辑电路的一种定时器信号技术，可以降低芯片功耗。时钟门控通过在电路中增加额外的逻辑单元、优化时钟树结构来节省电能。可以通过以下几种方式在设计中添加时钟门控逻辑：通过寄存器传输级编程中的条件选择来实现使能信号，从而在逻辑综合过程自动被翻译为时钟门控；通过实例化特殊的时钟门控单元，来把时钟门控插入到设计中去；使用专门的时钟门控工具添加。英语百科 Clock gating 时钟门控 Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree. Pruning the clock disables portions of the circuitry so that the flip-flops in them do not have to switch states. Switching states consumes power. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred.
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Clock gating