gate electrode

A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed.

Most of the radiation is not energetic enough to penetrate the gate electrode, so damage is confined to the periphery of that electrode.

The one gate insulating layer may be interposed between the common gate electrode and the one pair of fins of the semiconductor substrate.

So the name of a process became identified with the width of the gate electrode.

A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode.

A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.

The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.

and realizing the interconnection of the upper conducting wire and the lower conducting wire of the gate electrode after stripping.

In practical terms, this smallest feature was almost always the line that defined the gate electrode on the MOS transistor.

A semiconductor device may include a semiconductor substrate, one common gate electrode, and one gate insulating layer.

Following, forms dielectric layer on the base board, and the gate dielectric layer covers the gate electrode.

Each gate-electrode layer is connected with a respective separate gate contact (154, 156).

A gate electrode is formed to surround the vertical channel.

a gate electrode configured adjacent to the ditch, and a gate insulating layer is provided between the gate electrode and the ditch;

Disclosed herein is a semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film;

and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region;

using photoetching and stripping technologies to prepare the gate electrode of a device on the plastic substrate;

a sealing layer provided on the side opposite to the gate electrode, of the channel layer;

a first capacitor coupled between the gate electrode of the driving transistor and the first electrode of the driving transistor;

a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region;

stripping a needless gold thin film by acetone to obtain the gate electrode patterns of a device;

the gate electrode of the second enhancement type back-gate ZnO nanowire field effect transistor is connected to the second input terminal;

coating organic gate dielectric on the gate electrode by contact micro-zone spin coating in a device area;

an extension region formed in the semiconductor substrate on a source side of the gate electrode;

A semiconductor device includes first layer wiring including a gate electrode mounted on a substrate;

a gate insulating layer on the gate electrode, the gate insulating layer having an organic-inorganic hybrid material;

wherein the TFT comprises a first semiconductor layer, a grid electrode dielectric layer, a gate electrode layer;

an oxide semiconductor layer forming a channel region corresponding to the gate electrode;

a gate electrode arranged on the insulating layer, the gate electrode including a third opening connected to the second opening;

a gate insulating film provided between the gate electrode and the channel layer;

source and drain electrodes insulated from the gate electrode and connected to the second semiconductor layer;

photoetching again to obtain via hole patterns after dividing glue on the gate electrode;

a first gate insulating film formed on the substrate and the gate electrode, and including a silicon nitride film;

evaporating or depositing a layer of insulated medium layer material on the gate electrode;

The thin-film transistor includes: a gate electrode formed on a substrate;

a gate insulating layer to insulate the gate electrode from the first semiconductor layer and the second semiconductor layer;

a gate electrode insulated from the first semiconductor layer and the second semiconductor layer;

a source-drain diffusion layer formed on that surface of the semiconductor substrate which is adjacent to both sides of the gate electrode;

a gate electrode contacting the second layer region;