bit-lines

The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.

Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings.

A pair of first local lines id connected to the pair of bit lines by a first switching unit.

Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.

and then, discharging the metal bit lines with odd order coupled on the right side of the NROM memory cells to the common node.

Between the active patterns, word lines are arranged intersecting the bit lines.

A plurality of sub-arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines.

A secondary sense amplifier may be connected to the first and second global bit lines.

On the active patterns, bit lines are arranged to connect the drain regions along a direction.

The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo).

The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.

The source and bit lines are floating.

Similarly, a selected set of voltages on various word lines (70, 72, 74) and bit lines (80, 82, 84) are used to read the fuses (60-68).

A non-volatile memory device includes a cell array having memory cells arranged at intersections of word lines and bit lines;

several third bit lines for connecting the first bit lines;