bit line

A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells.

The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.

A first global bit line may be connected to a first one of the plurality of transistors.

The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.

The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bit line-bar (BLB).

The contact plug is electrically connected to the common doped region and the bit line is disposed over the substrate.

The impurity diffused region (20) is connected to a bit line (BL).

The negative potential applying circuit is connected to the first bit line and applies a negative potential to the first bit line.

For read operations, the wordline delays are summed with the bit line delays determined from edge column data to locate any outliers.

The first selection circuit connects the second bit line and the third bit line to the drain side bias circuit in a read operation mode.

Some problems such as static-noise margin(SNM) caused by reducing bit line voltage are also discussed in this paper.