| 单词 | clock skew |
| 释义 | 例句释义: 时钟脉冲相位差,时钟偏移,时钟偏差,时钟偏斜 1. Fix: The Kerberos authentication protocol requires that the clock skew between a server and a client is no greater than 5 minutes. 解决方案：Kerberos身份验证协议要求服务器和客户机之间的时钟差不大于5分钟。 www.ibm.com 2. In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance. 在多FPGA设计中，时钟信号的传输延时造成了FPGA间的大时钟偏差，进而制约系统性能。 www.dictall.com 3. Our basic idea is to make use of the permissible clock skew to enhance the timing reliability of a circuit. 我们的基本想法，是利用可允许的时序差异值来提高电路的时序可靠度。 www.ceps.com.tw 4. Preserving State with Feedback, Latches and Flip-flops, Clocks and Timing Constraints, Clock Skew. 用反馈，锁存，触发器保存状态，时钟，时序限制，时钟脉冲相位差。 www.myoops.org 5. Then we propose an algorithm to generate an optimal PD connection structures resulting in the minimum clock skew. 接著，我们提出一个能够产生最小时脉偏移之相差侦测器架构的演算法。 www.docin.com 6. A yield driven clock skew scheduling algorithm is proposed in presence of process variations. 针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。 www.dictall.com 7. Make: warning: Clock skew detected. Your build may be incomplete. 警告：检测到时钟错误。您的创建可能是不完整的。 bbs.chinaunix.net 8. Based on the layout static timing analysis, the clock period was optimized by the clock skew scheduling utilizing the DCCB. 利用此特性，基于电路版图时序分析，通过重构DCCB单元进行时钟偏差调整，优化时钟周期。 www.ceps.com.tw 9. The problem of delay-jitter and clock-skew in the network has a peat influence on the continuity of stream media's playing. 网络时延抖动以及时钟偏移等问题，会对媒体流播放是否流畅产生重要影响。 www.ceps.com.tw 10. The error messages you will get from clock skew will not generally be obvious. 在时钟问题中产生的错误消息通常都不太明显。 www.ibm.com 1. In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance. 在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。 www.dictall.com 2. How to reduce clock skew will be the most important topic of the clock synchronization circuit. 如何消除时脉偏移的问题，将成为重要的议题。 140.118.33.11:8080 3. Clock Skew Scheduling with Tolerance of Process Variations 抗工艺变化的时钟偏差规划 ilib.com.cn 4. Analysis of the Clock Skew in ASIC Design 专用集成电路设计中的时钟偏移分析 service.ilib.cn 5. A New Approach for Removing Clock Skew and Resets from One-Way Delay Measurement 一个消除单向时延测量中时钟频差和时钟重置的新方法 www.ilib.cn |
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