test vector

Real exchange rate; Mechanical&Electrical Products; Cointegration test; Vector auto-regression model.

the merged test mode can be used in carrying out testing actions defined by each test vector.

Simulation model build up and maintenance. Test vector generation.

can skillfully use Synopsys DC synthesizer and related test-vector generator.

To test open-circuit failures in CMOS circuits usually needs to use test vector pairs.

Study of an efficient SOC test vector compression scheme

Implementation of Automatic Test Vector Generation of Mixed-signal Current in Interconnect Test

Test Generation Algorithm Using Complete Test Vector of the Primitive Gates

Waveform Data Formats and Compressing Algorithms for Test Vector Translation

Research and Implementation of Key Technologies in Test Vector Cyclization

Dragging Mouse to Generate Test Vector of Digital Circuit Simulation and Fault Diagnosis

under the simulation environment of designing IC, compiling and linking the merged test vector generates merged test mode;

Produce of Generate Test Vector in the Testing of Digital Integrated Circuits

BIST Structure and Test Vector Generation Based on a Controlled LFSR

Research and Realization on Test Vector Translation Model Based on STIL

How to Generate Test Vector in the Testing of Digital Integrated Circuits