memory cell

Since then, the only brain of Woods all used to store the memory cell to odor discrimination of the object.

In a sense, a memory cell containing an address can be thought of as pointing to another memory cell. Such cells are called pointers.

A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputted in the semiconductor device.

The invention is directed to a resistive memory cell on a substrate and a resistive memory array.

Such integrated circuit includes a memory cell with a diode and an antifuse in communication with the diode.

A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained.

The advantage thereof is to reduce size of the memory cell, reduce programming interference, with paged erasing function.

and a decoder circuit configured to select a memory cell of the memory array in response to the second internal address.

A non-volatile memory cell operating at low voltage by means of impact ionization for programming.

This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell.

The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.

A memory cell is formed of a semiconductor junction diode interposed between conductors.

The area can be reduced by using such a memory cell.

and, a first word wire of the first direction that is connected to a word line node of the memory cell of the first line of the array.

A two-port SRAM memory cell (20) includes a pair of cross-coupled inverters (40) coupled to storage nodes.

A transistor is grounded not connected to GND without connection, thereby simplifying the replacement of data in the memory cell.

The generation mechanism of stress induced leakage current( SILC) in flash memory cell is studied by experiments.

A transistor memory cell can be made with any number of terminals.

Further, the memory cell is programmed utilizing a programming pulse that reverse biases the diode thereof.

The invention provides a memory cell transistor having multi-layer tunnel insulator and memory device.

The invention makes single memory cell possible to store multiple bits and increase memory capacity of cell.

The refresh portion reads and rewrites data from and in the memory cell in a power-down state.

This dissertation puts forward the implementation of a novel 4-transistor SRAM memory cell based on SOI technology.

Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

The circuit can also write information into the memory cell by selective write operation.

AIRS results in the memory cell pool after it is trained and classifies the original antigens by KNN.

The invention also discloses a reading and coding method of above OTP memory cell.

So silicon nanowires exhibit excellent application promising in nanoscale electron devices such as field effect transistor and memory cell.

The bigger the memory size, the longer it takes to index the memory cell.

After analyzing the weaknesses, we have revised combined structure memory cell in order to improve the performance.

This problem can occur if 70 (binary 1000110) has been changed to 6 (binary 000110) by an unstable memory cell.

In this paper, two kinds of standards CMOS technology memory cell structure are introduced.

Its memory cell survival time is longer.

The integrated circuit comprises: a semiconductor region for providing electric charge for altering a state of the nonvolatile memory cell;

The memory cell transistor comprises: an active region, the active region being elongated in a first direction of extension;

a dielectric, charge-trapping layer, for trapping and storing electric charge to define the state of the nonvolatile memory cell;

memory cell vaccine is extracted to antibodies for vaccination to accelerate the convergence of immune algorithm;

Design of a Low Voltage Switched-current Class AB Memory Cell

Decoherence Properties of Quantum Memory Cell in Squeezed Vaccum Reservoir

a first erasing wire of a first direction that is connected to the erasing grid of the memory cell in the first row of the array;

Generation mechanism of stress induced leakage current in flash memory cell

Analysis and Design of Memory Cell of Asynchronous FIFO