It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAMrefresh control, wait state generator and system reset logic.
The refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
3
While the internal reset signal is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller for refreshing data in DRAM is increased.