In embodiments of the present invention that include 3 or more delay paths, circuit 515 transmits multiple select signals to the multiplexer to select the appropriate delaypath.
在包括3个或更多延迟路径的本发明实施例中,电路515传输多个选择信号给乘法器以选择适当的延迟路径。
3
To improve the synthesis frequency, changes are made to the filter processing element. With pipelined vertical FIR and revised 2-level diagonal FIR, the corresponding delaypath can be shortened.