Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
2
The decision circuit of the chip is applied with a DFF using SCFL structure and its tuned phase shifter with differential current amplifiers according to the principle of vector addition.