At the Synthesis stage, we select the Top Down compile strategy, and suppose an ideal clock.
综合阶段采用的是自顶向下的编译策略，并虚拟理想时钟。
2
Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.
使用时钟作为资料在定时关闭已经创造各式各样的问题，特别在逻辑和物理综合。
3
The synthesis results show this FFT structure can run at 52mhz clock rate in XC4025E - 2. This FFT structure is easy to expand more points FFT structure.