Research has shown that most virtual invocations have only a single target for all receiver objects, and JIT compilers can generate more-efficient code for a direct call than for a virtual invocation.

With the same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly4 times than it implemented in direct way.

A better method for direct sequence spread spectrum (DSSS) receiver to decrease the acquisition time is proposed.