The low power consumption is obtained by using CMOS complementarylogic.
CMOS互补逻辑结构降低了电路的功耗。
2
We propose a novel architecture with error detection and error correction abilities called complementarylogic - alternating-complementarylogic (CL-ACL) structure.
提出了具有差错检测和校正能力的、延迟较小的互补-交替互补逻辑结构。
3
In this notation we have explicitly taken account of the fact that in normal operation, as we shall see, the logic levels at the output are complementary.