On the basis of the multiple-valued switch-level algebra, this paper proposes a logic design automation algorithm for NMOS and CMOS combinational circuits.
本文在多值开关级代数理论的基础上，提出了适合于NMOS及CMOS组合电路的逻辑设计自动化算法。
2
The test generation algorithm for non-robust path delay fault in combinational circuits is studied.
研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
3
This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.