This paper discusses extraction of the bit-synchronous signal with a first-order ADPLL mainly.
本文主要以一阶环为例讨论位同步信号提取。
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Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes.
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.