This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSIcircuits.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
2
As the geometric sizes of the components and devices in modern digital VLSIcircuits are especially reduced further, the noise influence on the VLSIcircuits tends to be remarkable.
特别指出了随着现代数字VL SI电路的元器件几何尺寸进一步缩小，其内部噪声的影响趋于显著。
3
They have a simple construction with low power dissipation and low output impedance and can be used as interfacing circuits in VLSI designs to reduce the number of external connections on a chip.