The systolic VLSI was designed to perform the new algorithm, followed by complexity analysis.
此外,为该算法设计出脉动阵列VLSI结构,并和现有结构进行了对比分析。
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To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
This structure divides wavefront control calculation into recursive algorithm and convolution algorithm, and maps them to respectively systolic array by using canonical mapping method.