A static verificationmethodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
2
A comparison of the static verificationmethodology with the dynamic verificationmethodology indicates that the former is more efficient and more accurate than the latter.
将这种验证方法与以往的动态验证方法进行了比较,结果表明,前者比后者更加高效和准确。
3
Experimental results show that the proposed methodology can effectively improve the verification quality and increase the verification efficiency.