The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本算法可直接结合到现有的RTL和门级网表的验证流程中，从而提高算术电路的验证能力。
2
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.