In an SISD architecture there is a single instruction cycle; operands are fetched serially into a single processing unit before execution.
在单指令流单数据流结构中，有单一的指令周期，在执行前，单个处理机按序取操作数。
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Because of this similarity, some methods from high-speed pipeline SISD computers can be extended to array processors or vector computers, and vice-versa.