This paper introduces a hysteresis comparator whose output can be delayed when the input signal is in rising time.
本文提出了一种在输入信号上升延迟滞的比较器电路。
2
Simulations have been done through adjusting parameters such as input signal amplitude, feedback gain, amplifier gain, comparator gain and the position of the phase compensator.
改变输入信号幅度、反馈增益系数、放大器增益、比较器增益等参数以及相位补偿器的位置进行了仿真。
3
The interrogation pulse, filter, signal amplifier, voltage comparator and the signal processing circuits are designed and realized.