If a mark is to be transmitted, the output goes high after the risingedge of the clock.
如果一个标志是要传输时,输出变为高电平后,在时钟的上升沿。
2
Data is read serially by the Driver IC on the input CLK risingedge once the STB input line goes low.
数据读取连续的驱动ic的输入时钟的上升沿一旦机顶盒输入线变低。
3
Phase Jitter: refers to the deviation of the FBKCLK risingedge to the REFCLK risingedge with respect to the average offset in a random sample of cycles.