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单词 sampling hold circuit
释义
sampling hold circuit
  • 简明释义
  • 取样保持电路
  • 网络释义
短语
  • 双语例句
  • 1
    Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
    采样速度和保持精度,是采样保持电路设计制作者最为关注的两项指标。
  • 2
    The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
    采样保持电路设计采用了电容下极板采样技术,不仅有效地避免了电荷注入效应引起的采样信号失真,而且消除了时钟馈通效应的不良影响。
  • 3
    Introduction sampling-hold circuit of a pipeline used for ADC.
    介绍一种用于流水线adc的采样保持电路。
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更新时间:2025/10/4 13:28:07