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单词 sample and hold circuit
释义
sample and hold circuit
  • 简明释义
  • 取样维持电路
  • 网络释义
  • 1

    ?取样保持电路

    ... sampling 5sB:mpliN v. 取样 sampling and hold circuit 取样保持电路 sampling bench 取样台 ...

  • 双语例句
  • 1
    Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
    采样速度和保持精度,是采样保持电路设计制作者最为关注的两项指标。
  • 2
    The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
    采样保持电路设计采用了电容下极板采样技术,不仅有效地避免了电荷注入效应引起的采样信号失真,而且消除了时钟馈通效应的不良影响。
  • 3
    The AD9446 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use.
    AD 9446是一款16位单芯片采样模数转换器(adc),内置一个片内采样保持电路,专门针对高性能、小尺寸和易用性进行了优化。
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更新时间:2025/8/5 22:21:14