With the signal from the master clock, the slaveclock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
从时钟利用主时钟发来的时钟信号,通过数字锁相环恢复出本地时钟信号。
2
It is shown by theory and case study that the master - slaveclock mode in a com munication system is ideal for proper functions of the current differential protection.
The micro-processor and VLSIC are core of the master clock, which consists of a control unit and can adjust all slave clocks (except standard time slaveclock) clockwise and inversion quickly.