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单词 sequential logic system
释义
sequential logic system
  • 简明释义
  • 时序逻辑系统
  • 网络释义
  • 1

    ?顺序逻辑系统

    ... 商业逻辑系统 Business Logic Systems 顺序逻辑系统 sequential logic system 数理逻辑系统 logistic system ...

  • 双语例句
  • 1
    Sequential logic synthesis is an important part of RTL synthesis system design.
    时序逻辑综合是RTL综合系统设计中的一个重要部分。
  • 2
    Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
    此外,为了避免高速时序电路中常见的时钟偏差,时钟通道采用负时钟偏差系统,并在时钟树中放置了缓冲器。
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更新时间:2025/3/27 10:59:30