So in order to reduce the number of PLL, the improved Equivalent pulse-counting method is proposed in view of the internal structure of the FPGA.
因此，为了减少锁相环的个数，针对FPGA的内部结构对该方法进行了改进，提出了改进等效脉冲计数法。
2
In this paper, the software and hardware achieved of equivalent pulsecounting and improved equivalent pulse-counting method are described in detail.
本文详细的介绍了等效脉冲计数法和改进等效脉冲计数法的软件以及硬件实现。
3
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.