The FSM model of target PCI businterface controller is then provided based on PCI bus operation timing.
根据PCI总线操作时序,提出了从设备接口控制器的有限状态机模型。
2
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.