The application of complex programmable logic device (CPLD) and digital programmabledelay line AD9501 in the system is described.
介绍了复杂可编程器件(CPLD)和可编程数字延迟线(AD95 0 1)在系统中的应用。
2
In this article, a programmable pulse delay unit based on EPLD is discussed.
文中讨论了基于EPLD的可编程脉冲延时单元。
3
In the case of FPGAs, the number of blocks used will also greatly influence the final delay after routing because most of the delays is the wiring delays due to the programmable interconnect existed.