Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negativeclock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
2
If this value is negative, the clock time is set back at the start of daylight saving time and advanced at the end.