This paper introduces the design and realization of a high-speed and low-cost virtual logic analyzer based on FPGA and USB2.0 bus.
本文介绍了一种基于FPGA的USB2.0高速、低成本的虚拟逻辑分析仪的设计原理与实现方法。
2
Level restoration pass-transistor logic is proposed for lowspeed cell while dynamic transmission gate logic for high speed cell.
低速单元采用带有电平恢复的传输管逻辑实现,高速单元采用动态传输门逻辑实现。
3
The product is specifically designed to provide well-regulated supply for low voltage IC applications such as high-speed bus termination and low current 3.3v logic supply.