The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for lowpowerlogic applications,’’ according to the firm.
本文显示立体型多栅结构可有效提升低功耗逻辑用III-V族QWFET管子的尺寸缩微能力。
2
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of lowpower flip-flop based on double edge trigger.
从消除时钟冗余,提高时钟利用率以达到降低功耗的思想出发,提出基于双边沿触发的触发器的逻辑设计。
3
This dissertation detailedly investigate the symbolic logic and some typical techniques for lowpower FSM logic synthesis and optimization.