The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for lowpowerlogic applications,’’ according to the firm.
本文显示立体型多栅结构可有效提升低功耗逻辑用III-V族QWFET管子的尺寸缩微能力。
2
This dissertation detailedly investigate the symbolic logic and some typical techniques for lowpower FSM logic synthesis and optimization.
论文详细讨论了低功耗有限状态机综合与优化中的符号逻辑和一些典型方法。
3
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of lowpower flip-flop based on double edge trigger.