The driving component includes: a N-bit serial buffer, a K-bit extension buffer, a N-bit video data buffer and N driving current output ports.

Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.

The second selected element selects one of the second groups of voltage references as an output analog voltage according to N-M least significant bits of the N-bit digital signal.