This paper proposes a high speed and low power pulselatch design, and integrates it to high speed DSP address generator.
提出了一种高速低功耗脉冲寄存器的设计方法，并将其应用在高速DSP地址生成单元的设计中。
2
In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch.
在实施例中，所述系统包含第一锁存器和经耦合以将时序信号提供给所述第一锁存器的脉冲产生器。
3
Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock.