In this embodiment, system memory controller 402 is integrated on the central processor 400 to provide access to system memory 404 through interconnect 406.

System memory controller 106, integrated on chipset 102 in one embodiment, provides central processor 100 access to the system memory subsystem 108 through interconnect 110.

In another embodiment, the graphics processor and graphics local memory controller are both located on the same integrated chip as the central processor (not shown).