In this embodiment, system memory controller 402 is integrated on the central processor 400 to provide access to system memory 404 through interconnect 406.

In one embodiment, graphics local memory controller is also integrated on chipset 408 to provide access to graphics local memory 416 through interconnect 418.

System memory controller 106, integrated on chipset 102 in one embodiment, provides central processor 100 access to the system memory subsystem 108 through interconnect 110.