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单词 gate level logic simulation
释义
gate level logic simulation
  • 简明释义
  • 门级逻辑模拟
  • 网络释义
  • 1

    [计]?门级逻辑模拟

    ... 门函数 gate function 门级逻辑模拟 gate level logic simulation 门级模拟 gate level simulation ...

  • 2

    ?闸位准逻辑仿真

    ... 闸反向器内存 gate inverter memory 闸位准逻辑仿真 gate level logic simulation 闸级模型 gate level model ...

短语
  • 双语例句
  • 1
    The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
    LOP电路设计采用VHDL语言门级描述,已通过逻辑仿真验证,并在浮点加法器的设计中得到应用。
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更新时间:2025/3/28 0:04:20