The gatecount of a system based on ERCCL can be significantly reduced, which, in turn, will decrease the energy loss.
所以一个基于ERCCL的系统可以大大减少逻辑门数，从而降低系统能耗。
2
As the average gatecount for designs now approaches or exceed on million, the verification has become the main bottleneck in design process.
随着设计规模的不断增加，芯片的平均设计门数已经超越百万级，验证已经成为设计流程中的主要瓶颈。
3
Adding parallelism typically increases gatecount, but the improved computational efficiency allows for the lower clock frequency needed to meet real-time constraints.