The dual ADC core features a multistage, differential pipelined architecture with integrated output errorcorrectionlogic.
这款双通道adc内核采用多级、差分流水线架构,并集成了输出纠错逻辑。
2
The principle of modulation, demodulation and data errorcorrection based on multi-valued logic is given in the text. And the expression of data errorcorrection is deduced.
文中给出了多值逻辑条件下数据的调制解调原理和纠错原理,并推导出数字就错的最终求解公式。
3
We propose a novel architecture with error detection and errorcorrection abilities called complementary logic - alternating-complementary logic (CL-ACL) structure.