The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).

Based on the analysis of the complexity and hardware architecture of FFT, the proposed processor adopts radix-4 DIF algorithm, pipelined architecture and fixed-point operation.

A physical processor is organized as different execution units at the hardware level, for example, fixed point and floating point operation units.