From system model selected, the lengths of hypothetical reference digital link and digital section are chosen, then the properties of bit error and jitter are determined.
从选定的模型，决定了假想参考数字通道和数字段的长度，确定了误码性能和抖动特性的指标。
2
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
3
Simulations show that adaptively modulated bit leaking method can reduce the jitter in pointer adjustment effectively in both the normal mode and the degraded mode of SDH network.